The escalating requirements for high density and performance (e.g., transistor and circuit speeds) associated with ultra-large scale integration ("ULSI") devices necessitate design rules for component features of 0.20 .mu.m and below, such as 0.15 .mu.m and below, such as source, drain, and gate regions and electrodes therefor formed in or on a common semiconductor substrate, challenges the limitations of conventional materials and manufacturing processes and necessitates use of alternative materials and development of new methodologies therefor.
An example of the above-mentioned challenge based upon the limitations inherent in conventional materials and methodologies utilized in the semiconductor integrated circuit ("IC") industry is the use of polysilicon for forming gate electrodes of metal-oxide-semiconductor ("MOS") transistors. Polysilicon is conventionally employed as a gate electrode material in MOS transistors in view of its good thermal stability, i.e., ability to withstand high temperature processing. More specifically, the good thermal stability of polysilicon-based materials permits high temperature annealing thereof during formation/activation of implanted source and drain regions. In addition, polysilicon-based materials advantageously block implantation of dopant ions into the underlying channel region of the transistor, thereby facilitating formation of self-aligned source and drain regions after gate electrode deposition/patterning is completed.
However, polysilicon-based gate electrodes incur a number of disadvantages, including, inter alia: (1) as device design rules decrease to below about 0.20 .mu.m, polysilicon gates are adversely affected by poly depletion, wherein the effective gate oxide thickness ("EOT") is increased. Such increase in EOT can reduce performance by about 15% or more; (2) polysilicon-based gate electrodes have higher resistivities than most metal or metallic materials and thus devices including polysilicon as electrode or circuit materials operate at a much slower speed than equivalent devices utilizing metalbased materials. Further, a significant portion of the voltage applied to the gate during operation is dropped in the polysilicon due to the poor conductivity of silicon. As a consequence, in order to compensate for the higher resistance, polysilicon-based materials require silicide processing in order to decrease their resistance and thus increase the operational speeds of polysilicon-based devices to acceptable levels; (3) use of polysilicon-based gates necessitates ion implantation of different dopant atoms for p-channel transistors and n-channel transistors formed in a CMOS device, which different dopant species are required for the p-channel and n-channel transistors to have compatible threshold voltages ("V.sub.t "). Disadvantageously, the threshold adjust implant is of sufficiently high doping concentration as to adversely impact the mobility of charge carriers in and through the channel region; and (4) polysilicon-based gate electrodes are less compatible with high dielectric constant ("high-k") materials (i.e., &gt;5, preferably &gt;20) which are desirable for use as gate oxide layers, vis-a-vis metalbased gate electrodes.
In view of the above-described drawbacks and disadvantages associated with the use of polysilicon-based materials as gate electrodes in MOS and CMOS transistor devices, several process schemes for making self-aligned MOS and/or CMOS transistor devices utilizing in-laid ("damascene") metal or metal-based gate electrodes have been proposed, such as are described in U.S. Pat. No. 4,745,082 (Kwok et al.); U.S. Pat. No. 5,447,874 (Grivna et al.); U.S. Pat. No. 5,960,270 (Misra et al.); and U.S. Pat. No. 6,033,963 (Huang et al.).
Metal or metal-based gate electrode materials offer a number of advantages vis-a-vis conventional polysilicon-based materials, including: (1) since many metal materials are mid-gap work function materials, the same metal gate material can function as a gate electrode for both n-channel and p-channel transistors in a CMOS process without adversely requiring threshold voltage (V.sub.t) adjust implants while maintaining V.sub.t at compatible levels; (2) metal gates allow the charge carrier mobility of the channel region to be improved since the channel region will no longer need high dose threshold implants and higher doping profiles in the MOS channel region; (3) metal gate electrodes have a greater conductivity than polysilicon electrodes and do not require complicated silicide processing in order to perform at high operational speeds; (4) unlike polysilicon-based gate electrodes, metal gate electrodes do not suffer from polysilicon depletion which affects the EOT of an MOS transistor, thereby affecting the performance of the MOS device (i.e., thinner EOTs, while possibly resulting in an increased leakage current, result in faster operating devices); (5) metal gate MOS devices are advantageous for use in fully-depleted silicon-on-insulator ("SOI") devices since V.sub.t of these devices can be more accurately controlled; and (6) metal gate electrodes are more compatible with high-k dielectrics than conventional polysilicon processing.
The use of metal or metallic materials as replacements for polysilicon-based materials as gate electrodes in MOS and/or CMOS devices incurs several difficulties, however, which difficulties must be considered and overcome in any metal-based gate electrode process scheme, including: (1) metal and/or metal-based gates cannot withstand the higher temperatures and oxidative ambients which conventional polysilicon-based gate electrode materials can withstand; (2) several candidate metals or metallic materials for use as gate electrodes do not exhibit adequate adhesion in film form to surrounding layers of different materials when these metals or metallic materials are patterned to very small geometries; (3) some metal or metallic films are difficult to lithographically pattern and etch via conventional processing techniques because etching thereof may significantly damage underlying oxides, thereby adversely affecting device performance; and (4) thermal processing subsequent to metal gate electrode formation may result in instability and degradation of the gate oxide due to chemical interaction between the metal and oxide at the metal gate-gate oxide interface.
An example of a suitable process sequence for forming an in-laid (or damascene) gate electrode is disclosed in U.S. Pat. No. 5,960,270, which process overcomes the above-enumerated difficulties associated with the use of metal or metal-based materials as gate electrodes in MOS and/or CMOS transistor devices, and is described below with reference to FIGS. 1-7. Briefly stated, according to this process, an in-laid, metal-gated MOS transistor is fabricated which comprises selfaligned source and drain electrodes which are formed before the in-laid metal gate electrode is formed. An opening is formed in a dielectric layer overlying a semiconductor substrate to define locations for source and drain regions, which source and drain regions are formed by thermally out-diffusing dopant atoms from overlying metal silicide regions, which metal silicide regions have been formed into source and drain segments in a self-aligned manner by formation of the opening in the dielectric layer. As a consequence, the source and drain regions are formed self-aligned to the opening in the dielectric layer, and the latter then subsequently filled with the metal or metal-based gate electrode material (after gate oxide formation by thermal oxidation of the substrate surface exposed through the opening). Since, according to this process scheme, doping of the source and drain regions is thermally driven and the source and drain regions are thermally activated before formation of the in-laid metal-based gate electrode, subjection of the latter to adverse thermal processing can be avoided.
Referring now to FIG. 1, a first process for fabricating an MOS transistor device 10 comprises providing a semiconductor substrate 12, typically a silicon (Si) wafer, in which trench-like dielectric 5 field isolation regions 14 are formed, as by conventional techniques, e.g., local oxidation of silicon ("LOCOS"), followed by formation of a p-type or n-type well region 16 in the substrate region intermediate adjacent field oxide regions 14. It should be recognized that, while in the figure, only one (1) well region is illustrated, a plurality of well regions of different conductivity type may be formed in the substrate for fabrication of, e.g., a CMOS device. In any event, after formation of the well region 16, an about 300-400 .ANG.thick silicide layer 18, preferably of either cobalt silicide (CoSi.sub.2) or nickel silicide (NiSi) is selectively formed overlying the well region 16, as by a selective growth process. The silicide layer 18 is doped with an appropriate conductivity type dopant, depending upon whether an NMOS or PMOS transistor is to be formed, either by ion implantation subsequent to its deposition or by in situ doping during deposition.
Referring now to FIG. 2, a thin (i.e., about 500 .ANG.thick) plasma-enhanced chemical vapor deposited ("PECVD") nitride layer 20 (utilized as an etch stop layer in subsequent processing) is then deposited so as to overlie the trench isolation regions 14 and the silicide layer 18. An about 1,000-4,000.ANG.thick (.about.2,000 .ANG. being preferred), low temperature dielectric oxide layer 22, e.g., of tetraethylorthosilicate ("TEOS") is then blanket-deposited over nitride layer 20.
Adverting to FIG. 3, an opening 24 is then formed in the oxide layer 22 overlying a central portion of well region 16, as by conventional photolithographic masking and etching techniques including plasma etching, the opening 24 extending through the nitride 20 and silicide 18 layers to expose at the bottom thereof a portion of the surface of semiconductor substrate 12. The opening 24 segments the silicide layer 18 into two separated portions, each of which is utilized for forming a respective underlying source or drain region of an MOS transistor in a following processing step.
Referring to FIG. 4, a thermal out-diffusion process is then performed for driving the dopant species out of the two silicide regions 18 to form respective underlying, fully self-aligned source and drain regions 26 and 28 within the substrate 12, the dopant species diffusing both vertically and laterally within the semiconductor substrate material. The doped silicide regions 18 remain in place for use as a portion of the source and drain electrodes, whereby the conductivity of these electrodes is enhanced.
As next illustrated in FIG. 5, an about 100 .ANG. thick layer 25 of a sacrificial oxide, e.g., a silicon oxide, is formed, as by thermal oxidation, on the surface of the semiconductor substrate 12 exposed at the bottom of opening 24, and sidewall spacers 23, typically of a silicon nitride (Si.sub.x N.sub.y), are formed on the internal wall surface of the opening 24, e.g., by conventional technigues. A threshold voltage (V.sub.t) adjust implant is then performed at a low ion implant energy to form V.sub.t adjust doped (i.e., implanted) region 31 within the portion of the well region 16 exposed through opening 24, after which the exposed portion of the sacrificial oxide layer 25 (i.e., the portion not covered by the sidewall spacers 23) is removed, as by etching. The spacers 23 provide, a necessary offset for not only compensating for lateral diffusion of the source and drain regions 26 and 28 but also for electrical isolation of subsequent gate electrode formations from the silicide regions 18, whereby Miller effects are reduced.
With reference to FIG. 6, a thermal oxidation of the exposed portion of the well region 18 is performed to form a thermal gate oxide layer 27 (or a high-k dielectric layer), and a metal or metal-containing electrically conductive material (e.g., comprising one or more of molybdenum (Mo), tungsten (W), titanium (Ti), aluminum (Al), tungsten silicide (WSi.sub.2), nickel silicide (NiSi), titanium nitride (TiN), and composites thereof, preferably selected on the basis of having a mid-gap work function so that the V.sub.t of both p-type and n-type transistors formed on the same substrate 12 are compatible) is deposited, via a suitable deposition process, to form a sufficiently thick blanket layer 28a filling the opening 24 and extending over the upper surface of dielectric layer 22.
Referring now to FIG. 7, the in-laid gate electrode process is completed by performing a planarization step, typically chemical-mechanical-polishing ("CMP"), for removing the portions of blanket layer 28a extending over the dielectric layer and for rendering the upper surface of the remaining electrically conductive plug 28b (constituting the gate electrode) co-planar with the upper, exposed surface of dielectric layer 22. Electrical contacts to the source and drain regions 26 and 28 may then be formed, as by conventional photolithographic masking and etching to form openings in dielectric layer 22 extending to the respective silicide layers 18, which openings are then filled with an electrically conductive material, e.g., a metal.
Another example of a suitable process sequence disclosed in U.S. Pat. No. 5,960,270 for forming an in-laid gate electrode for use in MOS and/or CMOS devices is described below with reference to FIGS. 8-16. Briefly stated, according to this process, a polysilicon or amorphous silicon ("a-Si") "dummy" or temporary gate electrode is formed and utilized as a mask for implanting self-aligned source and drain regions in the substrate. After formation of the source/drain regions, a dielectric layer is blanket-deposited and planarized (as by CMP) to expose a top portion of the dummy/temporary polysilicon or a-Si gate electrode. The polysilicon or a-Si dummy/temporary gate electrode is then removed to form a void where it was once located, which void is then filled with a metal gate electrode material, the latter being aligned to the source/drain regions by virtue of being formed in a location previously occupied by the self-aligned polysilicon or a-Si dummy/temporary gate.
Referring to FIG. 8, an initial step in the manufacture of semiconductor device 100 comprises formation of trench isolation regions 104 of a dielectric material in a suitable semiconductor substrate 102 (as in FIG. 1 of the first process), along with doped well regions 103 (i.e., at least one n-type well region and at least one p-type well region) for enabling CMOS device formation. A sacrificial thermal gate oxide layer 105 is formed over the upper surface of substrate 102 and then removed in order to yield a clean, active upper surface within the well region(s) 103.
Adverting to FIG. 9, a gate oxide layer 106 is formed on the exposed surface of well region 103, followed by sequential deposition thereon of a polysilicon dummy/temporary gate electrode 108 and an antireflective coating ("ARC") layer 110. The thus-obtained multi-layer structure is then subjected to photolithographic patterning/etching to form a dummy gate electrode stack.
With reference to FIG. 10, a sidewall gate oxidation is then performed to form sidewall oxidation layer 112, followed by formation thereon of tapered sidewall spacers 114, typically of a silicon nitride. Source and drain regions 118 are then formed in a self-aligned manner, as by conventional ion implantation and lightly doped drain ("LDD") processing.
Referring to FIG. 11, a refractory metal layer (e.g., of Co or Ti) is then deposited over the exposed upper surface of the thus-obtained structure and thermally reacted with the exposed silicon (Si) portions of the source and drain regions 118 to form an upper metal silicide layer 116 in contact with a portion of each of the source and drain regions. Silicide layer 116 does not form on the top of the polysilicon dummy gate electrode layer 108 due to the presence of the ARC layer 110.
In a following step, illustrated in FIG. 12, a nitride layer 120 is formed over the upper, exposed surface by a plasma enhanced deposition process, and a blanket-deposited dielectric layer 122 (e.g., a TEOS layer) deposited thereover to form an inter-level dielectric layer ("ILD") 120/122. Then, as shown in FIG. 13, a suitable planarization process, e.g., CMP, is performed on the ILD layer utilizing polysilcon layer 108 as a polishing stop, thereby exposing the top surface of polysilicon dummy/temporary gate electrode layer 108.
Referring now to FIG. 14, the polysilicon dummy/temporary gate electrode layer 108 is removed by means of a selective etching process (e.g., reactive ion etching ("RIE") in a chlorine (Cl.sub.2) plasma or wet polysilicon etching) to form a feature opening 124. V.sub.t is then optionally adjusted, as needed, by means of ion implantation through the feature opening 124 and the gate oxide layer 106 to form V.sub.t doped region 126. Gate oxide layer 106 is typically a sacrificial oxide layer which is removed and replaced with a high-k gate dielectric layer 125, as by thermal processing.
Adverting to FIG. 15, a metal or metal-based layer, e.g., of W, Mo, Ti, Al, TiN, WSi.sub.2, TiSi.sub.2, etc., is deposited as to fill the feature opening 124 and form a blanket or overburden layer 128a extending over the upper surfaces of the structure. In a following step, shown in FIG. 16, blanket or overburden layer 128a is planarized, as by CMP, to form a metal plug 128b filling the feature opening 124. Thus, metal gate electrode 128b is of substantially similar dimension and location as the dummy/temporary polysilicon gate electrode 108. As a consequence, the metal gate electrode 128b is self-aligned to the source/drain regions 118 formed within the substrate 102, as was dummy/temporary gate electrode 108.
In either of the above-described variants of in-laid metal gate electrode processing sequences, the ultimately formed gate oxide layer (27 or 125) is preferably comprised of a high-k dielectric material, inasmuch as such high-k dielectric materials advantageously provide greater coupling between the gate electrode and the underlying channel region of MOS transistors. However, the formation (e.g., deposition) and use of such high-k dielectric materials in the in-laid (or damascenetype) structures formed as part of the processing schemes (e.g., as shown in FIGS. 5-6 and 14-15) is difficult and problematic. Specifically, conventional high temperature methods for forming the high-k dielectric materials result in formation of a residue of high-k material on the sidewalls of the feature openings or apertures (24 or 124), which residue increases parasitic capacitance between the gate electrode and the source/drain regions. In addition, many high-k dielectric materials exhibit poor adhesion to Si and Si-based semiconductor substrate materials, as well as poor surface quality when in contact with Si-based materials.
For high-k dielectric materials (e.g., refractory metal oxides or silicates) to be optimally useful in in-laid metal gate MOS and CMOS transistor applications, it is necessary that gate dielectric layers fabricated therefrom have a smooth interface with the underlying semiconductor substrate (e.g., Si or Si-based), with a very low density of surface states. However, all of the methods conventionally employed (or proposed) for forming such high-k dielectric layers utilize chemical vapor deposition ("CVD") or physical vapor deposition ("PVD") processes which incur a number of disadvantages and drawbacks, including: (1) energetic ion bombardment accompanying PVD-type processing resulting in degradation of the oxide/Si interface; (2) presence of free oxygen during PVD- and/or CVD-type processing resulting in unwanted reaction with Si substrate material to form low-k SiO.sub.2 -based dielectric materials; and (3) entrapment of ion bombarded species during PVD-type processing, along with associated radiation damage of the deposited high-k dielectric films.
Accordingly, there exists a need for improved methodology for performing simple, reliable, and rapid formation of thin layers of dielectric materials (e.g., high-k oxides and/or silicates of refractory metals) for use as gate insulator layers in in-laid gate electrode MOS transistors and/or CMOS devices, which methodology avoids the drawbacks and disadvantages associated with the conventionally utilized CVD- and PVD-based methods and techniques and provides, inter alia, MOS transistors and/or CMOS devices exhibiting reduced parasitic capacitance between the gate and source/drain regions and improved transistor characteristics and properties.
The present invention, wherein a metal-based precursor for the high-k gate dielectric layer is electrolytically-deposited at a relatively low temperature in the absence of bombarding species or free oxygen and subsequently converted into a thin layer of a desired high-k dielectric material in a manner which substantially precludes access of oxygen to the semiconductor substrate/dielectric layer interface, effectively addresses and solves the need for improved methodology for the manufacture of high quality, in-laid gate (e.g., metal gate) MOS transistors and CMOS devices, while utilizing low cost processing techniques and apparatus. Further, the methodology provided by the present invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components requiring high quality dielectric layers for use as gate insulators.